1. Field of the Invention
This invention relates to the fabrication of a semiconductor devices and more specifically to semiconductor devices fabricated from silicon on insulator, (SOI), technology.
2. Description of Prior Art
The objective of the semiconductor industry to continually improve chip performance has in part been satisfied by the trend to micro-miniaturazation. The ability of specific semiconductor disciplines to reduce critical silicon chip shapes and images have allowed sub-micron features to be routinely achieved. Photolithograhy, via use of more sophisticated exposure cameras, as well an the development of more sensitive photoresist materials, has been a major contributor allowing micro-miniaturazation to occur. Reactive ion etching, (RIE), allowing for the successful transfer of these sub-micron images in photoresist, to underlying semiconductor materials; has also played a major role in the trend to micro-miniaturazation, The ability to produce smaller shapes results in reductions in parasitic capacitances, which in turn improve the performance of these devices. However the approach of increasing performance, via micro-miniaturization, can be ultimately limited by the ability of the specific semiconductor fabrication disciplines to continually construct smaller devices.
Another method used to increase device performance, via decreasing parasitic capacitances, is by the silicon on insulator, (SOD, technology. In this technology a thin layer of single crystalline silicon resides on a insulator. The active device regions are created within the single crystalline silicon, which overlies the insulator. Therefore the high junction capacitance, observed with devices fabricated without SOI is significantly decreased with SOI, due to the absence of junction capacitance associated with an underlying silicon substrate.
The advances in the SOI technology have created many opportunities for device designers, for both bipolar junction transistor, (BJT), as well as complimentary metal oxide semiconductor, (CMOS), applications. Furthermore the SOI technology allows an easier process sequence to be used for fabrication of bipolar--CMOS, (BiCMOS), designs. Prior art, such as Houston, et al, in U.S. Pat. No. 5,185,280, and lwamatsu, et al, in U.S. Pat. No. 5,294,281, have described methods for making integrated circuits using SOI However these inventions do not show the specific techniques used to produce competitive BJT devices, that this invention will teach. This invention will describe a process for fabricating lateral NPN, bipolar junction transistors, using SOI technology, with optimized device parameters, such as base to collector breakdown voltage, as well as transistor gain, beta, using process sequences normally used for the fabrication of metal oxide semiconductor field effect transistors, (MOSFET), devices, and therefore extendable for use in BiCMOS applications